Delay Testing of Asynchronous Noc Interconnects

Testing of chips built using deep sub-micron technology is becoming harder since crosstalk and small variations in the fabrication processes are adversely affecting circuit dynamic behaviour. The resulting logic and delay faults can only be detected using at-speed testing of the circuits. Faults resulting from crosstalk become more prominent among long links connecting two clock domains in a system designed using Globally Asynchronous Locally Synchronous (GALS) principles. In this paper we propose an efficient method for at-speed testing of delay faults in links used for handshaking based communication among GALS domains. Our method is conservative and has the property that it can detect all faulty chips but may also label some good chips as faulty with a small probability. It is possible to extend our method to combine it with functional testing of the link and adapt it for on-line testing.